附录A3:计数器、移位寄存器、FSM的输入和输出

Digital System Design using FSMs Pub Date : 2021-06-25 DOI:10.1002/9781119782735.app3

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Appendix A3: Counters, Shift Registers, Input, and Output with an FSM

© 2021 John Wiley & Sons Ltd. Published 2021 by John Wiley & Sons Ltd. Companion website: www.wiley.com/go/minns/digitalsystemdesign This appendix contains a number of techniques to help in the development of synchronous binary counters and shift registers. These are used in some of the designs covered in various chapters throughout this book. There is also an example of the memory tester FSM using the Logisim Simulator.

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Digital System Design using FSMs

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