1.8V CMOS斩波四象限模拟乘法器

2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST) Pub Date : 2017-05-01 DOI:10.1109/MOCAST.2017.7937649

Dimitrios Baxevanakis, P. Sotiriadis

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引用次数: 2

摘要

提出了一种1.8V CMOS斩波四象限模拟乘法器，用于低频信号处理。特别强调的是通过斩波稳定实现低输出噪声，而乘法器的操作是基于MOS跨线性原理。该设计已在TSMC 0.18µm CMOS工艺中实现和仿真。

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A 1.8V CMOS chopper four-quadrant analog multiplier

A 1.8V CMOS chopper four-quadrant analog multiplier, intending to serve as an autonomous IC block for low-frequency signal processing, is presented. Particular emphasis is laid upon achieving low output noise by means of chopper stabilization, while the multiplier's operation is based on the MOS Translinear Principle. The proposed design has been implemented and simulated in TSMC 0.18 µm CMOS process.

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2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)

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