Design of an Edge-Coded Signaling Transceiver with Minimal Inter-Symbol Separation

Applications such as the Internet of Things and Body Area Networks impose stringent footprint and power requirements on communication protocols that are difficult to meet using the widely used Clock and Data Recovery (CDR) transceivers. Although there have been efforts to devise alternative CDR architectures and implementation methods (digital or analog) to reduce their power/area impact, the presence of a CDR still poses significant challenges in terms of the serial link’s overall size and power consumption. Edge-Coded Signaling (ECS) is a recent CDR-less serial communication technique based on transmitting only the indices of the ON bits of data in the form of a sequence of pulses separated by an Inter-Symbol Spacing (ISS). ECS transceivers, in general, have proven to be superior in terms of size, power, and transmission reliability to CDR ones. However, in prior ECS prototypes, error-free transmission of ECS pulses with ISS less than four reference clock cycles has not been possible, effectively limiting the overall data rate. This paper proposes a modified implementation of the ECS transceiver, which relies on the same underlying principle but with improvements that allow error-free transmission with an ISS as small as one reference clock cycle, thus significantly increasing the effective data rate. An ASIC (65nm) and an FPGA implementation of the modified version show 53%, 60%, and 150% improvements in the minimum, average, and maximum data rates, respectively, at 25MHz. Moreover, the ASIC implementation shows a 4% and 25% reduction in area and power consumption, respectively, compared to the recent ECS prototypes.