高效的大电平时钟电路的最小区重定时

Proceedings Design, Automation and Test in Europe Pub Date : 1998-02-23 DOI:10.1109/DATE.1998.655956

N. Maheshwari, S. Sapatnekar

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引用次数: 6

摘要

延迟约束面积优化是超大规模集成电路合成中的一个重要步骤。最小面积(minarea)重定时是解决这一问题的一种有效技术。将采空区再定时问题表述为一个线性规划;在这项工作中，我们提出了减少该线性程序大小的技术以及生成该线性程序的有效技术。这为大型电平时钟电路(具有数万个门)提供了一种有效的极小区重定时方法。

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Efficient minarea retiming of large level-clocked circuits

Delay-constrained area optimization is an important step in synthesis of VLSI circuits. Minimum area (minarea) retiming is a powerful technique to solve this problem. The minarea retiming problem has been formulated as a linear program; in this work we present techniques for reducing the size of this linear program and efficient techniques for generating it. This results in an efficient minarea retiming method for large level-clocked circuits (with tens of thousands of gates).

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Proceedings Design, Automation and Test in Europe

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