C. Mesaritakis, G. Sarantoglou, S. Theodoridis, A. Bogris
{"title":"光子神经网格中的贝叶斯训练","authors":"C. Mesaritakis, G. Sarantoglou, S. Theodoridis, A. Bogris","doi":"10.1109/COMPENG50184.2022.9905470","DOIUrl":null,"url":null,"abstract":"Neural networks based on reconfigurable photonic integrated chips (RPICs) can offer zero-latency processing, marginal power consumption and operational flexibility. On the other hand, they are subject to, performance affecting, operational/fabrication deviations in their building blocks. Here, we present a Bayesian learning framework that when combined with device characterization, can dramatically decrease power consumption beyond 74% and significantly simplify the driving circuitry.","PeriodicalId":211056,"journal":{"name":"2022 IEEE Workshop on Complexity in Engineering (COMPENG)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Bayesian Training in Photonic Neural Meshes\",\"authors\":\"C. Mesaritakis, G. Sarantoglou, S. Theodoridis, A. Bogris\",\"doi\":\"10.1109/COMPENG50184.2022.9905470\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Neural networks based on reconfigurable photonic integrated chips (RPICs) can offer zero-latency processing, marginal power consumption and operational flexibility. On the other hand, they are subject to, performance affecting, operational/fabrication deviations in their building blocks. Here, we present a Bayesian learning framework that when combined with device characterization, can dramatically decrease power consumption beyond 74% and significantly simplify the driving circuitry.\",\"PeriodicalId\":211056,\"journal\":{\"name\":\"2022 IEEE Workshop on Complexity in Engineering (COMPENG)\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-07-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Workshop on Complexity in Engineering (COMPENG)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/COMPENG50184.2022.9905470\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Workshop on Complexity in Engineering (COMPENG)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/COMPENG50184.2022.9905470","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Neural networks based on reconfigurable photonic integrated chips (RPICs) can offer zero-latency processing, marginal power consumption and operational flexibility. On the other hand, they are subject to, performance affecting, operational/fabrication deviations in their building blocks. Here, we present a Bayesian learning framework that when combined with device characterization, can dramatically decrease power consumption beyond 74% and significantly simplify the driving circuitry.
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