用于时钟数据恢复电路的两级相位插补器

2020 IEEE International Conference on Artificial Intelligence and Information Systems (ICAIIS) Pub Date : 2020-03-01 DOI:10.1109/ICAIIS49377.2020.9194929

Dongxu Quan, Xiameng Lian

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引用次数: 0

摘要

基于相位插值的数字时钟数据恢复因其处理突发模式的能力而被广泛应用于数字时钟设计中。本文提出了一种基于IQ时钟的两级相位插补器。可以对第一级尾电流进行微调，以平衡第一级插补引起的幅度差。第二阶段操作8步相位插值使用时钟与45°的差异。该电路采用hlmc55nmdr工艺实现。DNL为0.8LSB, INL为2LSB，典型功耗为36.36mW@1.2V。PI工作频率为2.5G，其控制逻辑工作在312.5MHz。

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A 2-Stage Phase Interpolator Used in Clock Data Recovery Circuit

Phase interpolation based digital clock data recovery are widely adopted in Serdes design because of capability of dealing with burst mode. In this paper, a two-stage phase interpolator utilizing IQ clock are proposed. The tail current in first stage can be trimmed to equalized the amplitude difference caused by first stage interpolation. The second stage operates 8-step phase interpolation by using clock with 45° difference. The Circuit is implemented in HLMC 55nmdr process. The DNL is 0.8LSB, INL is 2LSB, typical power consumption is 36.36mW@1.2V. PI operating frequency is 2.5G and its control logic operates at 312.5MHz.

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2020 IEEE International Conference on Artificial Intelligence and Information Systems (ICAIIS)

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