Efficient implementation techniques for vector memory systems

Existing vector machines' memory systems use heavy interleaving and SRAM technology for faster data access. In this paper, we present an efficient vector memory architecture that adopts prime-degree memory interleaving and exploits the capabilities of new-generation DRAM chips with small SRAM cache. The major contribution of this paper is an incremental indexing scheme for prime-degree memory interleaving that takes at most two integer divisions as the initial start-up overhead for each logical vector memory access, and generates one bank/offset address pair per cycle thereafter. We have also developed a vector pre-fetching scheme that ensures that vector data elements are in the SRAM buffers before they are accessed, thus effectively masking the long delays associated with normal DRAM accesses.<>