{"title":"自适应网格路由芯片的设计","authors":"Jun-Woo Kang","doi":"10.1109/ICCS.1994.474248","DOIUrl":null,"url":null,"abstract":"Design of an adaptive router chip with minimum possible delay is described. The designed router is for message passing between computers which are connected in 2D mesh topology. The implemented algorithm is the negative-first adaptive wormhole routing algorithm which is deadlock free, livelock free, minimal, and maximally adaptive. The functional blocks of the router and asynchronous interfaces between routers were verified with VHDL modeling and simulation. Future enhancements for dynamic fault handling features are discussed.<<ETX>>","PeriodicalId":158681,"journal":{"name":"Proceedings of ICCS '94","volume":"199 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of adaptive mesh routing chip\",\"authors\":\"Jun-Woo Kang\",\"doi\":\"10.1109/ICCS.1994.474248\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Design of an adaptive router chip with minimum possible delay is described. The designed router is for message passing between computers which are connected in 2D mesh topology. The implemented algorithm is the negative-first adaptive wormhole routing algorithm which is deadlock free, livelock free, minimal, and maximally adaptive. The functional blocks of the router and asynchronous interfaces between routers were verified with VHDL modeling and simulation. Future enhancements for dynamic fault handling features are discussed.<<ETX>>\",\"PeriodicalId\":158681,\"journal\":{\"name\":\"Proceedings of ICCS '94\",\"volume\":\"199 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-11-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of ICCS '94\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCS.1994.474248\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of ICCS '94","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCS.1994.474248","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of an adaptive router chip with minimum possible delay is described. The designed router is for message passing between computers which are connected in 2D mesh topology. The implemented algorithm is the negative-first adaptive wormhole routing algorithm which is deadlock free, livelock free, minimal, and maximally adaptive. The functional blocks of the router and asynchronous interfaces between routers were verified with VHDL modeling and simulation. Future enhancements for dynamic fault handling features are discussed.<>
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