K. Torii, Y. Shimamoto, S. Saito, O. Tonomura, M. Hiratani, Y. Manabe, M. Caymax, J. Maes
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引用次数: 16
摘要
我们认为，在开发高/spl kappa/栅极电介质中，最重要的任务是设计接口以确保足够高的移动性和可靠性。考虑到100纳米节点，Al/sub 2/O/sub 3/在化学和热稳定性、势垒偏移以及与传统CMOS工艺的兼容性方面似乎是最有希望的候选者。Al/sub 2/O/sub 3/栅极电介质在sub-100 nm fet中的集成已经被证明;然而，由此产生的电子迁移率仅为SiO/sub - 2/栅极电介质场效应管的四分之一(D. Buchanan et al.， Tech. Digest IEDM, p. 223, 2000;李家辉等人，同上，第645页，2000)。我们已经从实验和理论上阐明了迁移率降低的机制。
The mechanism of mobility degradation in MISFETs with Al/sub 2/O/sub 3/ gate dielectric
We believe that the most important task in the development of high-/spl kappa/ gate dielectrics is to engineer the interface to assure high enough mobility and reliability. Considering the 100-nm node, Al/sub 2/O/sub 3/ would appear to be the most promising candidate in terms of chemical and thermal stability, barrier offset, and compatibility with the conventional CMOS process. The integration of Al/sub 2/O/sub 3/ gate dielectrics in sub-100 nm-FETs has already been demonstrated; however, the resulting electron mobility was only a quarter the value for a FET with SiO/sub 2/ gate dielectric (D. Buchanan et al., Tech. Digest IEDM, p. 223, 2000; J.H. Lee et al., ibid., p. 645, 2000). We have clarified the mechanism by which mobility is thus degraded, both experimentally and theoretically.
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