Carlos A. P. S. Martins, S. T. Kofuji, J. A. Zuffo, E. Moreno
{"title":"一种用于图像重建的VLSI架构","authors":"Carlos A. P. S. Martins, S. T. Kofuji, J. A. Zuffo, E. Moreno","doi":"10.1109/CCECE.1997.608281","DOIUrl":null,"url":null,"abstract":"In this paper we propose a VLSI architecture for an image reconstructor. The architecture implements in hardware the Two Dimensional Normalized Sampled Finite Sinc Reconstructor (NSFSR 2-D) reconstruction technique. Based on validation results, we conclude the proposed architecture implements correctly the NSFSR 2-D and is optimized in performance when compared with a software-based implementation.","PeriodicalId":359446,"journal":{"name":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A VLSI architecture for image reconstruction\",\"authors\":\"Carlos A. P. S. Martins, S. T. Kofuji, J. A. Zuffo, E. Moreno\",\"doi\":\"10.1109/CCECE.1997.608281\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we propose a VLSI architecture for an image reconstructor. The architecture implements in hardware the Two Dimensional Normalized Sampled Finite Sinc Reconstructor (NSFSR 2-D) reconstruction technique. Based on validation results, we conclude the proposed architecture implements correctly the NSFSR 2-D and is optimized in performance when compared with a software-based implementation.\",\"PeriodicalId\":359446,\"journal\":{\"name\":\"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-05-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CCECE.1997.608281\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CCECE.1997.608281","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper we propose a VLSI architecture for an image reconstructor. The architecture implements in hardware the Two Dimensional Normalized Sampled Finite Sinc Reconstructor (NSFSR 2-D) reconstruction technique. Based on validation results, we conclude the proposed architecture implements correctly the NSFSR 2-D and is optimized in performance when compared with a software-based implementation.