周期精确多核结构性能模拟器的设计

G. Wang, Zhang Tiefei, Like Yan, Xie Bin, Tianzhou Chen
{"title":"周期精确多核结构性能模拟器的设计","authors":"G. Wang, Zhang Tiefei, Like Yan, Xie Bin, Tianzhou Chen","doi":"10.1109/SEC.2008.19","DOIUrl":null,"url":null,"abstract":"As multi-core technology has become the trend to improve the performance of processor, there is more need to design a performance simulator for the design of multi-core architecture and for the evaluation of system performance. However there are few simulators that support different architectures of multi-core processor well. This paper presents a design and implementation of a cycle accurate multi-core processor architecture simulator, it is a component design, which can be customized to different multi-core architectures, furthermore, provides a practical tool for the design and evaluation of multi-core architecture.","PeriodicalId":231129,"journal":{"name":"2008 Fifth IEEE International Symposium on Embedded Computing","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"The Design of a Cycle Accurate Multi-core Architecture Performance Simulator\",\"authors\":\"G. Wang, Zhang Tiefei, Like Yan, Xie Bin, Tianzhou Chen\",\"doi\":\"10.1109/SEC.2008.19\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As multi-core technology has become the trend to improve the performance of processor, there is more need to design a performance simulator for the design of multi-core architecture and for the evaluation of system performance. However there are few simulators that support different architectures of multi-core processor well. This paper presents a design and implementation of a cycle accurate multi-core processor architecture simulator, it is a component design, which can be customized to different multi-core architectures, furthermore, provides a practical tool for the design and evaluation of multi-core architecture.\",\"PeriodicalId\":231129,\"journal\":{\"name\":\"2008 Fifth IEEE International Symposium on Embedded Computing\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-10-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 Fifth IEEE International Symposium on Embedded Computing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SEC.2008.19\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 Fifth IEEE International Symposium on Embedded Computing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SEC.2008.19","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

随着多核技术成为提高处理器性能的趋势,越来越需要设计一个性能模拟器来进行多核架构的设计和系统性能的评估。然而,很少有模拟器能够很好地支持不同的多核处理器架构。本文提出了一种周期精确的多核处理器体系结构模拟器的设计与实现,它是一种组件式设计,可针对不同的多核体系结构进行定制,为多核体系结构的设计与评估提供了实用的工具。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
The Design of a Cycle Accurate Multi-core Architecture Performance Simulator
As multi-core technology has become the trend to improve the performance of processor, there is more need to design a performance simulator for the design of multi-core architecture and for the evaluation of system performance. However there are few simulators that support different architectures of multi-core processor well. This paper presents a design and implementation of a cycle accurate multi-core processor architecture simulator, it is a component design, which can be customized to different multi-core architectures, furthermore, provides a practical tool for the design and evaluation of multi-core architecture.
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