{"title":"一种高效的极性码连续消列解码器","authors":"Huang-Chang Lee, Yi-Qin Zhang, Hsin-Yu Lee, Yeong-Luh Ueng","doi":"10.1109/ICCW.2019.8757183","DOIUrl":null,"url":null,"abstract":"Achieving a high decoding throughput using a successive cancellation list (SCL) decoder for polar codes is difficult due to its sequential decoding architecture. In this work, combining the local sorter from a single parity check (SPC) node with a shift-based path memory, a modified fast simplified successive cancellation list (Fast-SSCL) decoder is proposed, in order to provide a high-throughput using a low-complexity implementation. The proposed modified Fast-SSCL decoder can be operated at 470 MHz and was synthesized with an area of 5.26 mm<sup>2</sup> using a TSMC 90 nm CMOS process. The decoder presented in this work is able to improve the throughput to area ratio (TAR) by more than 30% compared with the previous designs.","PeriodicalId":426086,"journal":{"name":"2019 IEEE International Conference on Communications Workshops (ICC Workshops)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An Efficient Successive Cancellation List Decoder for Polar Codes\",\"authors\":\"Huang-Chang Lee, Yi-Qin Zhang, Hsin-Yu Lee, Yeong-Luh Ueng\",\"doi\":\"10.1109/ICCW.2019.8757183\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Achieving a high decoding throughput using a successive cancellation list (SCL) decoder for polar codes is difficult due to its sequential decoding architecture. In this work, combining the local sorter from a single parity check (SPC) node with a shift-based path memory, a modified fast simplified successive cancellation list (Fast-SSCL) decoder is proposed, in order to provide a high-throughput using a low-complexity implementation. The proposed modified Fast-SSCL decoder can be operated at 470 MHz and was synthesized with an area of 5.26 mm<sup>2</sup> using a TSMC 90 nm CMOS process. The decoder presented in this work is able to improve the throughput to area ratio (TAR) by more than 30% compared with the previous designs.\",\"PeriodicalId\":426086,\"journal\":{\"name\":\"2019 IEEE International Conference on Communications Workshops (ICC Workshops)\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-05-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE International Conference on Communications Workshops (ICC Workshops)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCW.2019.8757183\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE International Conference on Communications Workshops (ICC Workshops)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCW.2019.8757183","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An Efficient Successive Cancellation List Decoder for Polar Codes
Achieving a high decoding throughput using a successive cancellation list (SCL) decoder for polar codes is difficult due to its sequential decoding architecture. In this work, combining the local sorter from a single parity check (SPC) node with a shift-based path memory, a modified fast simplified successive cancellation list (Fast-SSCL) decoder is proposed, in order to provide a high-throughput using a low-complexity implementation. The proposed modified Fast-SSCL decoder can be operated at 470 MHz and was synthesized with an area of 5.26 mm2 using a TSMC 90 nm CMOS process. The decoder presented in this work is able to improve the throughput to area ratio (TAR) by more than 30% compared with the previous designs.
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