倒装芯片组件中焊点和分层的寿命

Z. Cheng
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引用次数: 11

摘要

采用热循环实验和有限元模拟相结合的方法,研究了下填料对不同凸点尺寸和凸点高度的两种类型(B和D)倒装芯片封装热力学行为的影响。结果表明:下填充剂的使用使SnPb焊点的热疲劳寿命大幅提高(/spl / sim/20倍),减弱了隔离高度对可靠性的影响,改变了封装的变形模式;结果表明,热疲劳裂纹发生在塑性应变范围最大的区域,对于有无下填料的包体,均可采用Coffin-Manson型方程。本文还研究了下填料的恒弹性(EC)、温度相关弹性(ET)和粘弹性(VE)等材料模型对倒装封装热力学行为的影响。VE模型的塑性应变范围较大,剪切方向位移较大,焊点寿命较低。ET模型的模拟结果与VE模型非常接近,可以代替VE模型进行简单的模拟。对低成本板上倒装芯片的下填层分层进行了分析。利用C-SAM对倒装芯片组件进行热循环加载,测量了芯片与下填料界面处的分层传播速率。实验测量分为B型细焊点和断口焊点、D型细焊点和断口焊点四种情况。在有限元模拟中,采用断裂力学方法计算了四种测量情况下的应变能释放率G和分层裂纹尖端附近的相位角/spl phi/。根据测量的分层传播速率和模拟的能量释放速率,确定了Paris半经验方程。同时,还模拟了不同分层裂纹长度下的能量释放率G。裂纹扩展时G /spl sim/ a曲线呈凸形,表明分层裂纹可能是稳定的。在传播一定长度后,裂纹将在倒装芯片组装中被阻止。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Lifetime of solder joint and delamination in flip chip assemblies
The effects of underfill on thermomechanical behaviors of two types (B and D) of flip chip packages, with different bumping size and stand-off height were investigated under thermal cycling by both experiments and finite element simulation. The results show that the use of underfill encapsulant increases tremendously (/spl sim/20 times) the thermal fatigue lifetime of SnPb solder joint, and weakens the effects of stand-off height on the reliability, and changes the deformation mode of the package. It was found that the thermal fatigue crack occurs in the region with a maximum plastic strain range, and the Coffin-Manson type equation could then be used for both packages with and without underfill. The effects of material models of underfill, i.e. constant elasticity (EC) and temperature dependent elasticity (ET) as well as the viscoelasticity (VE), on the thermomechanical behaviors of flip chip package were also studied in the simulation. The VE model gives comparatively large plastic strain range, and big displacements in shear direction, as well as sequentially low lifetime of solder joints. The ET model gives the close results to VE model and could be used instead of VE in simulations for the purpose of simplicity. Underfill delamination analysis of flip chip on low-cost board is also presented. The delamination propagation rates at the interface between chip and underfill have been measured by using C-SAM inspection of flip chip assemblies under thermal cycle loading. The experimental measurement was done in four cases, that were type B with fine solder joint and fractured solder joint, and type D with fine and fractured solder joint. In the finite element simulations the strain energy release rates G and the phase angles /spl phi/ near the delamination crack tip were calculated for four measurement cases by employing the fracture mechanical method. The Paris half-empirical equations were determined from the delamination propagation rates measured and the energy release rates simulated. Meanwhile, the energy release rates G with a different delamination crack length were also simulated. The G /spl sim/ a curve representing a convex shape when the crack propagates and indicates that the delamination crack may be stable. After propagating for a certain length the crack will be arrested in the flip chip assembly.
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