航空电子SDR应用的甚宽范围频率合成器结构

Z. A. A. Ismaili, W. Ajib, F. Gagnon, F. Nabki
{"title":"航空电子SDR应用的甚宽范围频率合成器结构","authors":"Z. A. A. Ismaili, W. Ajib, F. Gagnon, F. Nabki","doi":"10.1109/ICUWB.2015.7324527","DOIUrl":null,"url":null,"abstract":"This paper presents a very wide range frequency synthesizer architecture appropriate to avionic software defined radio (SDR) applications. The synthesizer generates a continuous carrier frequencies range between 187 MHz and 12.2 GHz that covers most of avionic communication applications. The covered range is distributed into twenty sub- bands by using a voltage controlled oscillator (VCO). The considered VCO is able to achieve a tuning range from 10 GHz to 12 GHz (18.2%) and from 7 GHz to 8.5 GHz (19.35%). It includes a capacitor bank, varactors, and switched inductors and is designed in 0.13 μm CMOS technology. Using the advanced design system (ADS) simulation tool and SpectreRF simulator, the proposed VCO exhibits a phase noise of -125 dBc/Hz at 12 GHz and at a 10 MHz offset frequency with a power consumption of 4.1 mW. At 10 GHz, the simulated synthesizer phase noise is of -102 dBc/Hz at a 1 MHz frequency offset. In addition, the loop bandwidth of the phase locked loop (PLL) is 1.1 MHz whereas the settling time is 3.64 μs.","PeriodicalId":339208,"journal":{"name":"2015 IEEE International Conference on Ubiquitous Wireless Broadband (ICUWB)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Very Wide Range Frequency Synthesizer Architecture for Avionic SDR Applications\",\"authors\":\"Z. A. A. Ismaili, W. Ajib, F. Gagnon, F. Nabki\",\"doi\":\"10.1109/ICUWB.2015.7324527\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a very wide range frequency synthesizer architecture appropriate to avionic software defined radio (SDR) applications. The synthesizer generates a continuous carrier frequencies range between 187 MHz and 12.2 GHz that covers most of avionic communication applications. The covered range is distributed into twenty sub- bands by using a voltage controlled oscillator (VCO). The considered VCO is able to achieve a tuning range from 10 GHz to 12 GHz (18.2%) and from 7 GHz to 8.5 GHz (19.35%). It includes a capacitor bank, varactors, and switched inductors and is designed in 0.13 μm CMOS technology. Using the advanced design system (ADS) simulation tool and SpectreRF simulator, the proposed VCO exhibits a phase noise of -125 dBc/Hz at 12 GHz and at a 10 MHz offset frequency with a power consumption of 4.1 mW. At 10 GHz, the simulated synthesizer phase noise is of -102 dBc/Hz at a 1 MHz frequency offset. In addition, the loop bandwidth of the phase locked loop (PLL) is 1.1 MHz whereas the settling time is 3.64 μs.\",\"PeriodicalId\":339208,\"journal\":{\"name\":\"2015 IEEE International Conference on Ubiquitous Wireless Broadband (ICUWB)\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-11-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Conference on Ubiquitous Wireless Broadband (ICUWB)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICUWB.2015.7324527\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Conference on Ubiquitous Wireless Broadband (ICUWB)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICUWB.2015.7324527","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8

摘要

提出了一种适用于航空电子软件无线电(SDR)应用的宽范围频率合成器结构。该合成器产生的连续载波频率范围在187mhz和12.2 GHz之间,覆盖了大多数航空电子通信应用。利用压控振荡器(VCO)将覆盖范围划分为20个子频带。所考虑的VCO能够实现10 GHz至12 GHz(18.2%)和7 GHz至8.5 GHz(19.35%)的调谐范围。它包括电容器组、变容管和开关电感,采用0.13 μm CMOS技术设计。利用先进的设计系统(ADS)仿真工具和SpectreRF模拟器,该VCO在12 GHz和10 MHz偏置频率下的相位噪声为-125 dBc/Hz,功耗为4.1 mW。在10ghz频率下,仿真合成器相位噪声为-102 dBc/Hz,频率偏移为1mhz。锁相环的环路带宽为1.1 MHz,稳定时间为3.64 μs。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Very Wide Range Frequency Synthesizer Architecture for Avionic SDR Applications
This paper presents a very wide range frequency synthesizer architecture appropriate to avionic software defined radio (SDR) applications. The synthesizer generates a continuous carrier frequencies range between 187 MHz and 12.2 GHz that covers most of avionic communication applications. The covered range is distributed into twenty sub- bands by using a voltage controlled oscillator (VCO). The considered VCO is able to achieve a tuning range from 10 GHz to 12 GHz (18.2%) and from 7 GHz to 8.5 GHz (19.35%). It includes a capacitor bank, varactors, and switched inductors and is designed in 0.13 μm CMOS technology. Using the advanced design system (ADS) simulation tool and SpectreRF simulator, the proposed VCO exhibits a phase noise of -125 dBc/Hz at 12 GHz and at a 10 MHz offset frequency with a power consumption of 4.1 mW. At 10 GHz, the simulated synthesizer phase noise is of -102 dBc/Hz at a 1 MHz frequency offset. In addition, the loop bandwidth of the phase locked loop (PLL) is 1.1 MHz whereas the settling time is 3.64 μs.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信