片上路由器的交通感知节能混合输入缓冲器设计

Yujie Gao, Yuan He, Xiaohan Yue, Haiyan Jiang, Xibo Wang
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引用次数: 0

摘要

在不断减少的功耗预算下,每个芯片的核心数量不断增加,推动了越来越复杂的片上网络(noc)的快速采用。在这种情况下,拥有更多的路由器或拥有更高基数的路由器是不可避免的,这会在已经消耗大量功率的情况下对输入缓冲区产生更高的需求。因此,本文介绍了一种混合输入缓冲器设计,用于片上路由器,试图在节省性能的同时减少其功耗。这个建议背后的关键思想是在设计输入缓冲区时考虑到网络流量的特征。正如我们的观察,大部分网络流量是短数据包,这意味着,使用缓慢但泄漏较少的设备(STT-MRAM)实现大多数输入缓冲区以抑制静态功耗是公平的,同时仍然将大多数网络流量存储在快速但泄漏的SRAM设备中以保持网络性能。我们的评估表明,这种混合设计可以在原始路由器面积的93.6%的情况下实现平均每飞行能耗降低44.5%,并且网络性能下降很小。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Traffic-Aware Energy-Efficient Hybrid Input Buffer Design for On-Chip Routers
A growing number of cores per chip has driven the rapid adoption of increasingly complex Networks-on-Chip (NoCs) under diminishing power budgets. In such a situation, having more routers or having routers with higher radix is inevitable, which creates higher demands for input buffers while they already draw a significant amount of power. Thus, this paper introduces a hybrid input buffer design for on-chip routers attempting to shrink their power consumption while conserving performance. The key idea behind this proposal is to design input buffers with the network traffic characteristics in mind. As in our observations, a large portion of the network traffic is short packets, which means, it is fair to implement most of the input buffers with slow but less leaky devices (STT-MRAM) to suppress the static power consumption while still having most of the network traffic stored in fast but leaky SRAM devices to conserve the network performance. Our evaluations show that this hybrid design can achieve an average reduction of energy consumption per flit by 44.5% under 93.6% of the original router area and small degradation of the network performance.
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