{"title":"带宽降低的H.264/AVC硬件设计采用各种窗口的无损压缩器和缓存方案","authors":"Chan-Sik Park","doi":"10.1109/ICCE.2009.5012302","DOIUrl":null,"url":null,"abstract":"The bus bandwidth insufficiency and the real-time processing of H.264/AVC are the most serious problems in High Definition(HD) or Ultra Definition(UD) video data. This paper presents the bandwidth reduced architecture to solve these problems. By using various windows of lossless compressor and cache scheme with each controller, we can significantly reduce both data bandwidth and processing cycles.","PeriodicalId":154986,"journal":{"name":"2009 Digest of Technical Papers International Conference on Consumer Electronics","volume":"103 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Bandwidth reduced H.264/AVC hardware design with various windows of lossless compressor and cache scheme\",\"authors\":\"Chan-Sik Park\",\"doi\":\"10.1109/ICCE.2009.5012302\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The bus bandwidth insufficiency and the real-time processing of H.264/AVC are the most serious problems in High Definition(HD) or Ultra Definition(UD) video data. This paper presents the bandwidth reduced architecture to solve these problems. By using various windows of lossless compressor and cache scheme with each controller, we can significantly reduce both data bandwidth and processing cycles.\",\"PeriodicalId\":154986,\"journal\":{\"name\":\"2009 Digest of Technical Papers International Conference on Consumer Electronics\",\"volume\":\"103 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-05-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 Digest of Technical Papers International Conference on Consumer Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCE.2009.5012302\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Digest of Technical Papers International Conference on Consumer Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCE.2009.5012302","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Bandwidth reduced H.264/AVC hardware design with various windows of lossless compressor and cache scheme
The bus bandwidth insufficiency and the real-time processing of H.264/AVC are the most serious problems in High Definition(HD) or Ultra Definition(UD) video data. This paper presents the bandwidth reduced architecture to solve these problems. By using various windows of lossless compressor and cache scheme with each controller, we can significantly reduce both data bandwidth and processing cycles.