{"title":"基于GPU的应用性能优化参数调优模型","authors":"Nhat-Phuong Tran, Myungho Lee","doi":"10.1109/FAS-W.2016.28","DOIUrl":null,"url":null,"abstract":"Recently, the Graphic Processing Units (GPUs) are becoming increasingly popular for the High Performance Computing (HPC) applications. Although the GPUs provide high peak performance, exploiting the full performance potential for application programs, however, leaves a challenging task to the programmers. When launching a parallel kernel of an application on the GPU, the programmer needs to carefully select the number of blocks (grid size) and the number of threads per block (block size) which greatly influence the performance. With a huge range of possible combinations of the parameter values, choosing the right grid size and the block size is not straightforward. In this paper, we propose a model for tuning the grid size and the block size through which we can reach the optimal performance. Our approach can significantly reduce the potential search space, instead of exhaustive search approaches in the previous research which are not practical in the real applications.","PeriodicalId":382778,"journal":{"name":"2016 IEEE 1st International Workshops on Foundations and Applications of Self* Systems (FAS*W)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Parameter Tuning Model for Optimizing Application Performance on GPU\",\"authors\":\"Nhat-Phuong Tran, Myungho Lee\",\"doi\":\"10.1109/FAS-W.2016.28\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Recently, the Graphic Processing Units (GPUs) are becoming increasingly popular for the High Performance Computing (HPC) applications. Although the GPUs provide high peak performance, exploiting the full performance potential for application programs, however, leaves a challenging task to the programmers. When launching a parallel kernel of an application on the GPU, the programmer needs to carefully select the number of blocks (grid size) and the number of threads per block (block size) which greatly influence the performance. With a huge range of possible combinations of the parameter values, choosing the right grid size and the block size is not straightforward. In this paper, we propose a model for tuning the grid size and the block size through which we can reach the optimal performance. Our approach can significantly reduce the potential search space, instead of exhaustive search approaches in the previous research which are not practical in the real applications.\",\"PeriodicalId\":382778,\"journal\":{\"name\":\"2016 IEEE 1st International Workshops on Foundations and Applications of Self* Systems (FAS*W)\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE 1st International Workshops on Foundations and Applications of Self* Systems (FAS*W)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/FAS-W.2016.28\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 1st International Workshops on Foundations and Applications of Self* Systems (FAS*W)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FAS-W.2016.28","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Parameter Tuning Model for Optimizing Application Performance on GPU
Recently, the Graphic Processing Units (GPUs) are becoming increasingly popular for the High Performance Computing (HPC) applications. Although the GPUs provide high peak performance, exploiting the full performance potential for application programs, however, leaves a challenging task to the programmers. When launching a parallel kernel of an application on the GPU, the programmer needs to carefully select the number of blocks (grid size) and the number of threads per block (block size) which greatly influence the performance. With a huge range of possible combinations of the parameter values, choosing the right grid size and the block size is not straightforward. In this paper, we propose a model for tuning the grid size and the block size through which we can reach the optimal performance. Our approach can significantly reduce the potential search space, instead of exhaustive search approaches in the previous research which are not practical in the real applications.