基于可编程逻辑器件的脉冲位置调制系统设计

Yuting Liu
{"title":"基于可编程逻辑器件的脉冲位置调制系统设计","authors":"Yuting Liu","doi":"10.1117/12.2640750","DOIUrl":null,"url":null,"abstract":"A communication system for remote communication is designed. The system uses FPGA as the main control unit and pulse position modulation PPM as the basic modulation mode. Aiming at the problem that frame synchronization can not be realized in PPM communication, this design adopts the way of adding frame head frame tail structure and inserting protection gap to ensure information synchronization. In addition, the four-phase clock synchronization extraction method is used in the synchronous demodulation of PPM signal at the receiving end, which effectively reduces the error rate of FPGA in the working process, and greatly simplifies the design of the whole system. In this design, the encoding of PPM will use Gray code mapping to reduce the bit error rate. Finally, the system achieves a faster communication rate, and the BER of the actual test is low.","PeriodicalId":336892,"journal":{"name":"Neural Networks, Information and Communication Engineering","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of pulse position modulation system based on programmable logic device\",\"authors\":\"Yuting Liu\",\"doi\":\"10.1117/12.2640750\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A communication system for remote communication is designed. The system uses FPGA as the main control unit and pulse position modulation PPM as the basic modulation mode. Aiming at the problem that frame synchronization can not be realized in PPM communication, this design adopts the way of adding frame head frame tail structure and inserting protection gap to ensure information synchronization. In addition, the four-phase clock synchronization extraction method is used in the synchronous demodulation of PPM signal at the receiving end, which effectively reduces the error rate of FPGA in the working process, and greatly simplifies the design of the whole system. In this design, the encoding of PPM will use Gray code mapping to reduce the bit error rate. Finally, the system achieves a faster communication rate, and the BER of the actual test is low.\",\"PeriodicalId\":336892,\"journal\":{\"name\":\"Neural Networks, Information and Communication Engineering\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Neural Networks, Information and Communication Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1117/12.2640750\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Neural Networks, Information and Communication Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1117/12.2640750","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

设计了一种远程通信系统。该系统以FPGA为主控单元,以脉冲位置调制PPM为基本调制方式。针对PPM通信中无法实现帧同步的问题,本设计采用增加帧头帧尾结构和插入保护间隙的方式来保证信息同步。此外,在接收端对PPM信号进行同步解调时采用了四相时钟同步提取方法,有效降低了FPGA在工作过程中的错误率,大大简化了整个系统的设计。在本设计中,PPM的编码将使用Gray码映射来降低误码率。最后,系统实现了更快的通信速率,实际测试的误码率较低。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design of pulse position modulation system based on programmable logic device
A communication system for remote communication is designed. The system uses FPGA as the main control unit and pulse position modulation PPM as the basic modulation mode. Aiming at the problem that frame synchronization can not be realized in PPM communication, this design adopts the way of adding frame head frame tail structure and inserting protection gap to ensure information synchronization. In addition, the four-phase clock synchronization extraction method is used in the synchronous demodulation of PPM signal at the receiving end, which effectively reduces the error rate of FPGA in the working process, and greatly simplifies the design of the whole system. In this design, the encoding of PPM will use Gray code mapping to reduce the bit error rate. Finally, the system achieves a faster communication rate, and the BER of the actual test is low.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信