Reversible implementation of square-root circuit

In this paper we present a novel reversible implementation of a square-root circuit with an array structure. In scientific computations such as numerical analysis, computer graphics, complex number computations, square root is an important operation. In classical irreversible arena we find different realizations of square root circuit. Since reversible circuit is emerging as an alternative to classical circuit, here we introduce a novel reversible realization of this operation. As a basic module, we propose a reversible controlled adder/subtractor (RCAS) block based on 2's Complement computation. In our design we use an array of such RCAS blocks which perform addition or subtraction based on the result generated from digit-by-digit square root operation. To our best knowledge this is the first methodical approach for implementing reversible square root circuit. The new structure of the circuit and different parameters — number of gates, garbage bits and quantum cost for n-bit realization is presented here.