A Journey from STIL to Verilog

With the growing complexity of System-On-Chips (SoCs), and the explosion of test data volume, test patterns validation is becoming a mandatory and crucial step. With modern large designs, detecting most issues at the level of the ATE is no longer a viable solution. Recent approaches rely on dedicated tools and flows prior to tester to validate test patterns, and reserve ATE to only screening real defect issues on the test-chip. This allows for early detection of successive and cumulative modeling and processing steps. In [1] we presented an original simulation-based patterns validation approach. A crucial step in that approach was the translation from cycle-based tester domain to an event-based simulation domain. This paper focuses on that part by presenting an approach for efficient and trustful translation of a STIL file to an equivalent HDL (Verilog) representation. To the best of our knowledge, this is the first paper that describes a full and detailed tester based language (STIL) to an HDL (Verilog) translation, thereby expressing fully and accurately the behavior of cycle based domain into an event-based environment. Such transformation allows porting the problem from tester domain to HDL and logic simulation domain, and exploiting their capabilities for sake of efficient validation, but also, debug, coverage and functional tests. The proposed approach is an industry proven methodology that was successfully implemented and exploited by an EDA tool [2] that is now used by several semiconductors companies for their daily pattern validation flows.