A 1.2V 0.1–3GHz software-defined radio receiver front-end in 130nm CMOS

A 1.2V 0.1–3GHz software-defined radio (SDR) receiver front-end in 130nm CMOS is presented. The current-driven passive mixer with 25% duty-cycle LO and reconfigurable inverter-based RF transconductor array (TCA) is utilized to satisfy the low 1/f noise and high linearity requirements. The current buffer is implemented as a like Tow-Thomas transimpedance biquad amplifier (TIA) with built-in 2nd-order filtering and reconfigurable gain/bandwidth. The scaling power consumption along with the gain and bandwidth is achieved by utilizing the switchable amplifier approach during TCA and TIA design. The measured results show that the front-end could provide reconfigurable conversion gain from 35dB to 55dB and signal bandwidth from 3MHz to 65MHz with scaling current consumption from 14.5mA to 48.5mA, from a power supply of 1.2V. The measured noise figure (NF) and output third-order intercept point (OIP3) with the maximum gain is 3.5∼6dB and higher than 10dBm, respectively, across 0.1∼3GHz frequency range, and the die area is 2.0×1.2 mm2.