Novel 21-level Reduced Switches Inverter

This article demonstrates the performance of an asymmetrical multilevel inverter configuration with fewer power electronics switches and dc voltage sources. The 21-level inverter designed to used only three input DC-link voltage sources and ten power electronics switch to obtained higher voltage level, better utilization of dc sources is also obtained, which can improve inverter TSV, cost, and efficiency. Thus, the number of DC sources is maintained smaller and is utilized so that the peak output voltage is nearly the sum of the input dc voltages. In addition, the output voltage levels are obtained by addition and subtraction of the input dc sources, which lower the number of dc sources and the inverter TSV. Moreover, the number of conducting switches is much lesser of the others MLIs, which results in smaller conduction loss and better efficiency. A carrier-based level-shifted PWM (LSPWM) technique is implemented using DS1103 based digital controller for the inverter. Finally, the experimental results of the inverter with dc-link voltage ratios are presented for RL load. Moreover, the performance of the MLI is compared with the existing MLI topologies.