高性能($\text{EOT} < 0.4\text{nm}$， Jg ~ 10−7 A/cm2) ald沉积Ru\SrTiO3堆栈，用于新一代DRAM柱式电容器

2018 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2018-12-01 DOI:10.1109/IEDM.2018.8614673

M. Popovici, A. Belmonte, H. Oh, G. Potoms, J. Meersschaut, O. Richard, H. Hody, S. Van Elshocht, R. Delhougne, L. Goux, G. Kar

{"title":"高性能($\\text{EOT} < 0.4\\text{nm}$， Jg ~ 10−7 A/cm2) ald沉积Ru\\SrTiO3堆栈，用于新一代DRAM柱式电容器","authors":"M. Popovici, A. Belmonte, H. Oh, G. Potoms, J. Meersschaut, O. Richard, H. Hody, S. Van Elshocht, R. Delhougne, L. Goux, G. Kar","doi":"10.1109/IEDM.2018.8614673","DOIUrl":null,"url":null,"abstract":"We demonstrate the fabrication of strontium titanate (STO) based metal-insulator-metal (MIM) capacitors with very-high dielectric constant (k∼118) and low leakage of 10−7 A/cm2 at ±1V for a ∼11nm thick dielectric using Ru as bottom electrode (BE) and top electrode (TE). The k enhancement is attributed to the formation of an ultrathin cubic SrRuO3 phase at the Ru/STO bottom interface, acting as a template optimizing the STO crystal quality from the interface to the bulk. This interface quality is evidenced by the same k∼118 extracted from STO thickness series and relating to the bulk-k value. This achievement opens up an alternative integration roadmap for DRAM capacitors, moving from the current cup-shape to a denser pillar-shape design.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"High-performance ($\\\\text{EOT} < 0.4\\\\text{nm}$, Jg∼10−7 A/cm2) ALD-deposited Ru\\\\SrTiO3 stack for next generations DRAM pillar capacitor\",\"authors\":\"M. Popovici, A. Belmonte, H. Oh, G. Potoms, J. Meersschaut, O. Richard, H. Hody, S. Van Elshocht, R. Delhougne, L. Goux, G. Kar\",\"doi\":\"10.1109/IEDM.2018.8614673\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We demonstrate the fabrication of strontium titanate (STO) based metal-insulator-metal (MIM) capacitors with very-high dielectric constant (k∼118) and low leakage of 10−7 A/cm2 at ±1V for a ∼11nm thick dielectric using Ru as bottom electrode (BE) and top electrode (TE). The k enhancement is attributed to the formation of an ultrathin cubic SrRuO3 phase at the Ru/STO bottom interface, acting as a template optimizing the STO crystal quality from the interface to the bulk. This interface quality is evidenced by the same k∼118 extracted from STO thickness series and relating to the bulk-k value. This achievement opens up an alternative integration roadmap for DRAM capacitors, moving from the current cup-shape to a denser pillar-shape design.\",\"PeriodicalId\":152963,\"journal\":{\"name\":\"2018 IEEE International Electron Devices Meeting (IEDM)\",\"volume\":\"121 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE International Electron Devices Meeting (IEDM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2018.8614673\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2018.8614673","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

我们演示了钛酸锶(STO)基金属-绝缘体-金属(MIM)电容器的制造，该电容器具有非常高的介电常数(k ~ 118)和低漏10−7 A/cm2，在±1V下，厚度为~ 11nm，使用Ru作为底电极(BE)和顶电极(TE)。k的增强是由于在Ru/STO底部界面处形成了超薄的立方SrRuO3相，作为模板优化了从界面到本体的STO晶体质量。从STO厚度系列中提取的相同k ~ 118证明了这种界面质量，并且与bulk-k值有关。这一成就为DRAM电容器开辟了一个可选的集成路线图，从目前的杯形转向更密集的柱形设计。

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High-performance ($\text{EOT} < 0.4\text{nm}$, Jg∼10−7 A/cm2) ALD-deposited Ru\SrTiO3 stack for next generations DRAM pillar capacitor

We demonstrate the fabrication of strontium titanate (STO) based metal-insulator-metal (MIM) capacitors with very-high dielectric constant (k∼118) and low leakage of 10−7 A/cm2 at ±1V for a ∼11nm thick dielectric using Ru as bottom electrode (BE) and top electrode (TE). The k enhancement is attributed to the formation of an ultrathin cubic SrRuO3 phase at the Ru/STO bottom interface, acting as a template optimizing the STO crystal quality from the interface to the bulk. This interface quality is evidenced by the same k∼118 extracted from STO thickness series and relating to the bulk-k value. This achievement opens up an alternative integration roadmap for DRAM capacitors, moving from the current cup-shape to a denser pillar-shape design.

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2018 IEEE International Electron Devices Meeting (IEDM)

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