T. Shibata, M. Konda, Y. Yamashita, T. Nakai, T. Ohmi
{"title":"基于神经元- mos的实时事件识别关联硬件","authors":"T. Shibata, M. Konda, Y. Yamashita, T. Nakai, T. Ohmi","doi":"10.1109/MNNFS.1996.493777","DOIUrl":null,"url":null,"abstract":"Neuron MOS transistor (/spl upsi/MOS) mimicking the fundamental behavior of neurons at a very primitive device level has been applied to construct a real-time event recognition hardware. A neuron MOS associator searches for the most similar event in the past memory to the current event based on Manhattan distance calculation and the minimum distance search by a winner take all (WTA) circuitry in a fully parallel architecture. A unique floating-gate analog EEPROM technology has been developed to build a vast memory system storing the events in the past. Test circuits of key subsystems were fabricated by a double-polysilicon CMOS process and their operation was verified by measurements as well as by simulation. As a simple application of the basic architecture, a motion-vector-search hardware was designed and fabricated. The circuit can find out the two-dimensional motion vector in about 150 nsec by a very simple circuitry.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"36 3","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Neuron-MOS-based association hardware for real-time event recognition\",\"authors\":\"T. Shibata, M. Konda, Y. Yamashita, T. Nakai, T. Ohmi\",\"doi\":\"10.1109/MNNFS.1996.493777\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Neuron MOS transistor (/spl upsi/MOS) mimicking the fundamental behavior of neurons at a very primitive device level has been applied to construct a real-time event recognition hardware. A neuron MOS associator searches for the most similar event in the past memory to the current event based on Manhattan distance calculation and the minimum distance search by a winner take all (WTA) circuitry in a fully parallel architecture. A unique floating-gate analog EEPROM technology has been developed to build a vast memory system storing the events in the past. Test circuits of key subsystems were fabricated by a double-polysilicon CMOS process and their operation was verified by measurements as well as by simulation. As a simple application of the basic architecture, a motion-vector-search hardware was designed and fabricated. The circuit can find out the two-dimensional motion vector in about 150 nsec by a very simple circuitry.\",\"PeriodicalId\":151891,\"journal\":{\"name\":\"Proceedings of Fifth International Conference on Microelectronics for Neural Networks\",\"volume\":\"36 3\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-02-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Fifth International Conference on Microelectronics for Neural Networks\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MNNFS.1996.493777\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MNNFS.1996.493777","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Neuron-MOS-based association hardware for real-time event recognition
Neuron MOS transistor (/spl upsi/MOS) mimicking the fundamental behavior of neurons at a very primitive device level has been applied to construct a real-time event recognition hardware. A neuron MOS associator searches for the most similar event in the past memory to the current event based on Manhattan distance calculation and the minimum distance search by a winner take all (WTA) circuitry in a fully parallel architecture. A unique floating-gate analog EEPROM technology has been developed to build a vast memory system storing the events in the past. Test circuits of key subsystems were fabricated by a double-polysilicon CMOS process and their operation was verified by measurements as well as by simulation. As a simple application of the basic architecture, a motion-vector-search hardware was designed and fabricated. The circuit can find out the two-dimensional motion vector in about 150 nsec by a very simple circuitry.