TEDOP: A Tiny Event-Driven Neural Network Hardware Core Enabling On-Chip Spike-Driven Synaptic Plasticity

For edge intelligent applications, this work proposes a tiny neuromorphic hardware core embedding high-speed on-chip synaptic plasticity, by adopting the proposed Temporal-Integrate neuron model and a simplified supervised spike-driven synaptic plasticity rule for on-chip learning. The proposed hardware core was prototyped on a very-low-cost Zybo Zynq-7010 FPGA device, and attained comparably high classification accuracies on many datasets (e.g. 90.4% on MNIST), with a learning and inference speed as high as 11,268 and 11,749 f $r$ ame/s, respectively, while dissipating only 39 mW power under a 250 MHz clock frequency.