电荷捕获NAND闪存器件的评述

H. Lue, S. Lai, T. Hsu, Y. Hsiao, P. Du, Szu-Yu Wang, K. Hsieh, R. Liu, Chih-Yuan Lu
{"title":"电荷捕获NAND闪存器件的评述","authors":"H. Lue, S. Lai, T. Hsu, Y. Hsiao, P. Du, Szu-Yu Wang, K. Hsieh, R. Liu, Chih-Yuan Lu","doi":"10.1109/ICSICT.2008.4734663","DOIUrl":null,"url":null,"abstract":"This paper carefully analyzes various charge-trapping NAND Flash devices including SONOS, MANOS, BE-SONOS, BE-MANOS, and BE-MAONOS. The erase mechanisms using electron de-trapping or hole injection, and the role of the high-k top dielectric (Al2O3) are critically examined. In addition to the intrinsic charge-trapping properties, the STI edge geometry in the NAND array also plays a crucial role in determining the programming/erasing and reliability characteristics. Erase saturation and incremental-step-pulse programming (ISPP) characteristics are strongly affected by the STI edge effects. Our analysis of recent progress provides a clear understanding to charge-trapping NAND devices and serves as a guideline for future development.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"A critical review of charge-trapping NAND flash devices\",\"authors\":\"H. Lue, S. Lai, T. Hsu, Y. Hsiao, P. Du, Szu-Yu Wang, K. Hsieh, R. Liu, Chih-Yuan Lu\",\"doi\":\"10.1109/ICSICT.2008.4734663\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper carefully analyzes various charge-trapping NAND Flash devices including SONOS, MANOS, BE-SONOS, BE-MANOS, and BE-MAONOS. The erase mechanisms using electron de-trapping or hole injection, and the role of the high-k top dielectric (Al2O3) are critically examined. In addition to the intrinsic charge-trapping properties, the STI edge geometry in the NAND array also plays a crucial role in determining the programming/erasing and reliability characteristics. Erase saturation and incremental-step-pulse programming (ISPP) characteristics are strongly affected by the STI edge effects. Our analysis of recent progress provides a clear understanding to charge-trapping NAND devices and serves as a guideline for future development.\",\"PeriodicalId\":436457,\"journal\":{\"name\":\"2008 9th International Conference on Solid-State and Integrated-Circuit Technology\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-12-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 9th International Conference on Solid-State and Integrated-Circuit Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSICT.2008.4734663\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.2008.4734663","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 13

摘要

本文仔细分析了各种电荷捕获NAND闪存器件,包括SONOS、MANOS、BE-SONOS、BE-MANOS和BE-MAONOS。采用电子脱陷或空穴注入的擦除机制,以及高k顶部电介质(Al2O3)的作用进行了严格的研究。除了固有的电荷捕获特性外,NAND阵列中的STI边缘几何形状在决定编程/擦除和可靠性特性方面也起着至关重要的作用。擦除饱和和增量步进脉冲规划(ISPP)特性受到STI边缘效应的强烈影响。我们对最近进展的分析提供了对电荷捕获NAND器件的清晰理解,并为未来的发展提供了指导。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A critical review of charge-trapping NAND flash devices
This paper carefully analyzes various charge-trapping NAND Flash devices including SONOS, MANOS, BE-SONOS, BE-MANOS, and BE-MAONOS. The erase mechanisms using electron de-trapping or hole injection, and the role of the high-k top dielectric (Al2O3) are critically examined. In addition to the intrinsic charge-trapping properties, the STI edge geometry in the NAND array also plays a crucial role in determining the programming/erasing and reliability characteristics. Erase saturation and incremental-step-pulse programming (ISPP) characteristics are strongly affected by the STI edge effects. Our analysis of recent progress provides a clear understanding to charge-trapping NAND devices and serves as a guideline for future development.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信