器件缩放对V-NAND中电子横向迁移机制的影响

2019 Silicon Nanoelectronics Workshop (SNW) Pub Date : 2019-06-01 DOI:10.23919/SNW.2019.8782947

Changbeom Woo, Shinkeun Kim, Jaeyeol Park, Hyungcheol Shin

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引用次数: 3

摘要

在本文中，我们使用TCAD模拟分析了V-NAND在保留操作中发生的依赖几何参数缩放的横向迁移(LM)机制。对LM进行了建模，分析了用于建模的时间常数(τ)参数的行为。此外，我们还根据邻词线(WLNei)的状态分析了保留特征。比较不同模式提取的τ，棋盘模式(C/P)的τ最小，其次是NPN和实体模式(S/P)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Effect of Device Scaling on Lateral Migration Mechanism of Electrons in V-NAND

In this paper, we analyzed lateral migration (LM) mechanism of V-NAND occurring during retention operation depending on scaling of geometric parameters using TCAD simulation. Modeling for LM was performed and the behavior of time-constant (τ) parameter used for modeling was analyzed. In addition, we analyzed retention characteristics according to the states of neighbor word line (WLNei.). Comparing the extracted τ for different patterns, checker-board pattern (C/P) has the smallest τ, followed by NPN and solid pattern (S/P).

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2019 Silicon Nanoelectronics Workshop (SNW)

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