基于ISA的功能测试生成及其在RISC处理器自检中的应用

2006 IEEE Design and Diagnostics of Electronic Circuits and systems Pub Date : 2006-04-18 DOI:10.1109/DDECS.2006.1649575

V. V. Belkin, S. Sharshunov

{"title":"基于ISA的功能测试生成及其在RISC处理器自检中的应用","authors":"V. V. Belkin, S. Sharshunov","doi":"10.1109/DDECS.2006.1649575","DOIUrl":null,"url":null,"abstract":"This paper presents a method for functional test generation, which aims self-test of RISC processors and processor cores. The method allows developing compact and quite effective software based tests if only the instruction set architecture (ISA) or ISA together with some micro architecture features are known. We have successfully applied this methodology to test a RISC processor core","PeriodicalId":158707,"journal":{"name":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"ISA Based Functional Test Generation with Application to Self-Test of RISC Processors\",\"authors\":\"V. V. Belkin, S. Sharshunov\",\"doi\":\"10.1109/DDECS.2006.1649575\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a method for functional test generation, which aims self-test of RISC processors and processor cores. The method allows developing compact and quite effective software based tests if only the instruction set architecture (ISA) or ISA together with some micro architecture features are known. We have successfully applied this methodology to test a RISC processor core\",\"PeriodicalId\":158707,\"journal\":{\"name\":\"2006 IEEE Design and Diagnostics of Electronic Circuits and systems\",\"volume\":\"52 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-04-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE Design and Diagnostics of Electronic Circuits and systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DDECS.2006.1649575\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Design and Diagnostics of Electronic Circuits and systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DDECS.2006.1649575","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

本文提出了一种针对RISC处理器和处理器内核自测的功能测试生成方法。只要知道指令集体系结构(ISA)或ISA与一些微体系结构特征，该方法就可以开发出紧凑且非常有效的基于软件的测试。我们已经成功地将这种方法应用于测试RISC处理器核心

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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ISA Based Functional Test Generation with Application to Self-Test of RISC Processors

This paper presents a method for functional test generation, which aims self-test of RISC processors and processor cores. The method allows developing compact and quite effective software based tests if only the instruction set architecture (ISA) or ISA together with some micro architecture features are known. We have successfully applied this methodology to test a RISC processor core

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来源期刊

2006 IEEE Design and Diagnostics of Electronic Circuits and systems

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