Design of nano scale CMOS full adder with low leakage and ground bounce noise reduction

As the technology is continuously scaled down towards nano scale regime, several techniques related to optimization of the leakage power dissipation is presented recently in the research papers. Transistor gating is a very effective way to reduce leakage power, but this technique is having a limitation, when circuit transits from sleep to active mode, it produces the large voltage fluctuations on ground terminal because of the residual charge stored during the sleep mode. These fluctuations are referred to as ground bounce noise (GBN), It disturbs the normal operation of the circuit due to the disturbance in the logic states in the internal nodes which reduces reliability of the circuit. GBN is the serious problem in ultra-deep submicron technology because it can change the logic level of the internal nodes. In this paper we have presented an effective and reliable sleep circuit to reduce the problem of GBN, The new circuit uses three NMOS transistors and one PMOS transistor. To test the efficacy of the proposed sleep circuit, one bit conventional full adder is tested with extensive post layout simulations at 45nm technology. Result shows that it reduces the leakage power, approximately 99% and GBN reduces approximately 57.4% as compared to the existing sleep circuits.