并发多访问数据结构的性能分析与建模

A. Rukundo, A. Atalar, P. Tsigas
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引用次数: 0

摘要

扩展并发数据结构的主要障碍是访问共享数据结构访问点时的内存争用,这会导致线程序列化,阻碍并行性。为了解决这一挑战,文献中大量的工作已经提出了提高并发数据结构并行性的多访问技术。然而,对并发多访问数据结构的执行行为进行分析和建模的工作很少,特别是在共享内存设置中。本文对共享内存环境下并发多访问数据结构的一般执行行为进行了分析和建模。我们研究和分析了两种流行的随机访问模式的行为:共享(远程)和独占(本地)访问,以及设计无锁数据结构的两种最常用的原子原语的行为:比较和交换,以及Fetch和Add。我们通过将线程执行过程划分为五个逻辑会话来建模并发多访问:I)旁工,ii)接入点搜索,iii)接入点采集,iv)接入点数据采集,v)接入点数据操作。我们将接入点的获取建模为具有并行服务器的封闭排队网络系统,并根据数据在内存系统中的位置进行数据获取。我们在一组并发数据结构设计上评估了我们的模型,包括计数器、堆栈和FIFO队列。该评估是在两种最先进的多核处理器上进行的:英特尔至强Phi CPU 7290具有72个物理核和英特尔至强E5-2695具有14个物理核。我们的模型能够在两种架构上以80%到100%的准确率预测给定并发数据结构的吞吐量性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Performance Analysis and Modelling of Concurrent Multi-access Data Structures
The major impediment to scaling concurrent data structures is memory contention when accessing shared data structure access-points, leading to thread serialisation, hindering parallelism. Aiming to address this challenge, significant amount of work in the literature has proposed multi-access techniques that improve concurrent data structure parallelism. However, there is little work on analysing and modelling the execution behaviour of concurrent multi-access data structures especially in a shared memory setting. In this paper, we analyse and model the general execution behaviour of concurrent multi-access data structures in the shared memory setting. We study and analyse the behaviour of the two popular random access patterns: shared (Remote) and exclusive (Local) access, and the behaviour of the two most commonly used atomic primitives for designing lock-free data structures: Compare and Swap, and, Fetch and Add. We model the concurrent multi-accesses by splitting the thread execution procedure into five logical sessions: i) side-work, ii) access-point search iii) access-point acquisition, iv) access-point data acquisition and v) access-point data operation. We model the acquisition of an access-point, as a system of closed queuing networks with parallel servers, and data acquisition in terms of where the data is located within the memory system. We evaluate our model on a set of concurrent data structure designs including a counter, a stack and a FIFO queue. The evaluation is carried out on two state of the art multi-core processors: Intel Xeon Phi CPU 7290 with 72 physical cores and Intel Xeon E5-2695 with 14 physical cores. Our model is able to predict the throughput performance of the given concurrent data structures with 80% to 100% accuracy on both architectures.
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