一种利用CMOS充电半浮栅器件的新型三元开关元件

35th International Symposium on Multiple-Valued Logic (ISMVL'05) Pub Date : 2005-05-19 DOI:10.1109/ISMVL.2005.5

H. Gundersen, R. Jensen, Y. Berg

{"title":"一种利用CMOS充电半浮栅器件的新型三元开关元件","authors":"H. Gundersen, R. Jensen, Y. Berg","doi":"10.1109/ISMVL.2005.5","DOIUrl":null,"url":null,"abstract":"In this paper we present a novel voltage mode non-inverting CMOS semi floating-gate (SFG) ternary switching element. The design is applicable for reconstructing or refreshing ternary logic signals. The switching points are tuned using capacitive division. A preliminary simulation results from Cadence Spectre with AMS 0.35 /spl mu/m process parameters c35b4 is included.","PeriodicalId":340578,"journal":{"name":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","volume":"258 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A novel ternary switching element using CMOS recharge semi floating-gate devices\",\"authors\":\"H. Gundersen, R. Jensen, Y. Berg\",\"doi\":\"10.1109/ISMVL.2005.5\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we present a novel voltage mode non-inverting CMOS semi floating-gate (SFG) ternary switching element. The design is applicable for reconstructing or refreshing ternary logic signals. The switching points are tuned using capacitive division. A preliminary simulation results from Cadence Spectre with AMS 0.35 /spl mu/m process parameters c35b4 is included.\",\"PeriodicalId\":340578,\"journal\":{\"name\":\"35th International Symposium on Multiple-Valued Logic (ISMVL'05)\",\"volume\":\"258 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-05-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"35th International Symposium on Multiple-Valued Logic (ISMVL'05)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.2005.5\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"35th International Symposium on Multiple-Valued Logic (ISMVL'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.2005.5","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 8

摘要

本文提出了一种新型的电压模式非反相CMOS半浮栅(SFG)三元开关元件。该设计适用于三元逻辑信号的重构或刷新。开关点是用电容分割调谐的。本文给出了Cadence Spectre在AMS 0.35 /spl mu/m工艺参数c35b4上的初步仿真结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A novel ternary switching element using CMOS recharge semi floating-gate devices

In this paper we present a novel voltage mode non-inverting CMOS semi floating-gate (SFG) ternary switching element. The design is applicable for reconstructing or refreshing ternary logic signals. The switching points are tuned using capacitive division. A preliminary simulation results from Cadence Spectre with AMS 0.35 /spl mu/m process parameters c35b4 is included.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

35th International Symposium on Multiple-Valued Logic (ISMVL'05)

自引率

0.00%

发文量