CMOS集成电路静电致潜在损伤的研究

1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173) Pub Date : 1900-01-01 DOI:10.1109/RELPHY.1998.670562

Y. Huh, M.G. Lee, J. Lee, H. Jung, T. Li, D. Song, Y. Lee, J. Hwang, Y. Sung, S. Kang

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引用次数: 20

摘要

CMOS集成电路在累积低强度静电放电后的潜在损伤已经得到了深入的研究。在不同的ESD应力模式下，对封装级晶体管的潜在损伤进行了研究。使用64mb DRAM芯片作为DUT，还评估了潜在损坏对电路性能下降的影响。

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A study of ESD-induced latent damage in CMOS integrated circuits

ESD-induced latent damage in CMOS integrated circuits has been thoroughly investigated after cumulative low-level ESD stress. A study of the latent damage for transistors at the package level has been performed with various kinds of ESD stress modes. The impact of latent damage on circuit performance degradation was also evaluated using a 64 Mb DRAM chip as a DUT.

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来源期刊

1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173)

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