A Feedforward and Feedback Constant-Slope Digital-to-Time Converter in 28nm CMOS Achieving ≤ 0.12% INL/Range over >100mV Supply Range

Advanced techniques focusing on ultra-low jitter and spurs in integer-N PLLs, such as subsampling, injection locking and type-I architectures, have been extensively explored in the last decade. To accommodate new communication protocols, it is more attractive to push these high performance PLLs to a fractional-N operation. One major issue related to the fractional-N PLLs are fractional spurs, especially the in-band spurs that cannot be simply filtered out by the PLL loop but which can ruin the spectral performance. Phase interpolators (PI) and digital-to-time converters (DTC) are commonly used to assist in reducing the phase detection quantization error. The linearity, range, jitter and power are the main trade-offs in these blocks’ design. A DTC with >9-b (<0.2% INL/range) linearity is favored in the fractional-N PLLs targeting <-50dBc in-band fractional spurs. This work presents techniques to minimize the nonlinearities and power in the proposed constant slope DTC. Figure 1 shows the complete schematic of the proposed design. With feedforward (FF) and feedback (FB) techniques and nonlinearity cancellation, the implemented DTC runs at 50MHz and features 543ps delay range, 0.11% INL/Range, 36uW power consumption.