一种用于Delta-Sigma ADC的168db高增益折叠级联码运算放大器

Jing Kai, Yu Ningmei, Quan Xing
{"title":"一种用于Delta-Sigma ADC的168db高增益折叠级联码运算放大器","authors":"Jing Kai, Yu Ningmei, Quan Xing","doi":"10.1109/ICIEA.2019.8834023","DOIUrl":null,"url":null,"abstract":"A fully differential CMOS folded cascode operational amplifier is presented. It uses gain boosting technique on both NMOS and PMOS branch to enhance total gain. New current-sink topology is used to maximally enhance the open-loop gain as well as not to deteriorate the output swing badly. Local small area but good-performance CT-CMFB is adopted in gain-boosted auxiliary amplifier to optimize both area cost and calibration performance. An improved SC-CMFB is used on total amplifier output to stabilize the output common mode node voltage as well as not to impact differential gain performance. Designed in low-cost UMC 110 nm process with a 5V supply voltage, simulation results show DC gain of 164.1 dB and a phase margin of 63 degree at a unity gain bandwidth of 17.09 MHz. The static current is 174 uA along with achieved PSRR of 186.5dB, making it suitable in high-performance Delta-Sigma ADCs.","PeriodicalId":311302,"journal":{"name":"2019 14th IEEE Conference on Industrial Electronics and Applications (ICIEA)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 168 dB high gain folded cascode operational amplifier for Delta-Sigma ADC\",\"authors\":\"Jing Kai, Yu Ningmei, Quan Xing\",\"doi\":\"10.1109/ICIEA.2019.8834023\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fully differential CMOS folded cascode operational amplifier is presented. It uses gain boosting technique on both NMOS and PMOS branch to enhance total gain. New current-sink topology is used to maximally enhance the open-loop gain as well as not to deteriorate the output swing badly. Local small area but good-performance CT-CMFB is adopted in gain-boosted auxiliary amplifier to optimize both area cost and calibration performance. An improved SC-CMFB is used on total amplifier output to stabilize the output common mode node voltage as well as not to impact differential gain performance. Designed in low-cost UMC 110 nm process with a 5V supply voltage, simulation results show DC gain of 164.1 dB and a phase margin of 63 degree at a unity gain bandwidth of 17.09 MHz. The static current is 174 uA along with achieved PSRR of 186.5dB, making it suitable in high-performance Delta-Sigma ADCs.\",\"PeriodicalId\":311302,\"journal\":{\"name\":\"2019 14th IEEE Conference on Industrial Electronics and Applications (ICIEA)\",\"volume\":\"80 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 14th IEEE Conference on Industrial Electronics and Applications (ICIEA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICIEA.2019.8834023\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 14th IEEE Conference on Industrial Electronics and Applications (ICIEA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIEA.2019.8834023","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

提出了一种全差分CMOS折叠级联码运算放大器。在NMOS支路和PMOS支路上均采用增益增强技术来提高总增益。采用了新的电流吸收拓扑,最大限度地提高了开环增益,同时不会严重恶化输出摆幅。在增益增强辅助放大器中采用局部小面积但性能良好的CT-CMFB,优化了面积成本和校准性能。改进的SC-CMFB用于总放大器输出,以稳定输出共模节点电压,同时不影响差分增益性能。采用低成本UMC 110 nm工艺设计,电源电压为5V,在17.09 MHz的单位增益带宽下,直流增益为164.1 dB,相位裕度为63度。静态电流为174 uA, PSRR为186.5dB,适用于高性能Delta-Sigma adc。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 168 dB high gain folded cascode operational amplifier for Delta-Sigma ADC
A fully differential CMOS folded cascode operational amplifier is presented. It uses gain boosting technique on both NMOS and PMOS branch to enhance total gain. New current-sink topology is used to maximally enhance the open-loop gain as well as not to deteriorate the output swing badly. Local small area but good-performance CT-CMFB is adopted in gain-boosted auxiliary amplifier to optimize both area cost and calibration performance. An improved SC-CMFB is used on total amplifier output to stabilize the output common mode node voltage as well as not to impact differential gain performance. Designed in low-cost UMC 110 nm process with a 5V supply voltage, simulation results show DC gain of 164.1 dB and a phase margin of 63 degree at a unity gain bandwidth of 17.09 MHz. The static current is 174 uA along with achieved PSRR of 186.5dB, making it suitable in high-performance Delta-Sigma ADCs.
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