设计进行卷积器

L. Dadda, V. Piuri, R. Stefanelli
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引用次数: 2

摘要

提出了一种多并行卷积器设计方案,该方案基于对p并行卷积器同时输入的p个相邻样本的并发处理。该方案使用p个单元,每个单元接收输入样本,每p个样本产生一次卷积;这些被称为p相子卷积。给出并讨论了p相子卷积器和整个p平行卷积器的详细设计。该方案可用于每个采样的位并行和位串行输入表示。p-并联卷积器的输入采样率是使用相同积分技术实现的标准(1-并联)卷积器采样率的p倍。p-并联卷积器所需的组件数大约是标准卷积器所需组件数的p倍
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Multi-parallel convolvers
A scheme for a convolver design, called a multiparallel convolver, that is based on concurrent processing of p adjacent samples that are input simultaneously to the p-parallel convolver is presented. The scheme uses p units, each of which receives the input samples and produces one convolution every p samples; these are called p-phase subconvolvers. The detailed design of the p-phase subconvolvers and of the whole p-parallel convolver is presented and discussed. The scheme can be used for both the bit-parallel and the bit-serial input presentation of each sample. The input sample rate of the p-parallel convolver is p times the sample rate of a standard (1-parallel) convolver implemented using the same integration technology. The number of components required by a p-parallel convolver is approximately p times the number of components required by a standard convolver.<>
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