具有SoC架构的用于多媒体内容分析的万亿级性能图像流处理器

Tse-Wei Chen, Chi-Sun Tang, Sung-Fang Tsai, Chen-Han Tsai, Shao-Yi Chien, Liang-Gee Chen
{"title":"具有SoC架构的用于多媒体内容分析的万亿级性能图像流处理器","authors":"Tse-Wei Chen, Chi-Sun Tang, Sung-Fang Tsai, Chen-Han Tsai, Shao-Yi Chien, Liang-Gee Chen","doi":"10.1109/ASSCC.2009.5357149","DOIUrl":null,"url":null,"abstract":"A 1.0 TOPS image stream processor, which deals with image processing tasks for multimedia content analysis, is implemented with 2.2mm2 area in 90nm CMOS technology. Two sub processors, linear processor and order processor, are integrated to achieve tera-scale performance. In the proposed SoC architecture, the data are transferred between processors and the high bandwidth dual memory through the local media bus, which reduces the power consumption in the AHB data access. Based on the memory architecture, the maximum input data rate of the proposed image stream processor reaches 62.5 Gpixel/s, which meets the requirements for real-time HDTV image processing.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Tera-scale performance image stream processor with SoC architecture for multimedia content analysis\",\"authors\":\"Tse-Wei Chen, Chi-Sun Tang, Sung-Fang Tsai, Chen-Han Tsai, Shao-Yi Chien, Liang-Gee Chen\",\"doi\":\"10.1109/ASSCC.2009.5357149\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 1.0 TOPS image stream processor, which deals with image processing tasks for multimedia content analysis, is implemented with 2.2mm2 area in 90nm CMOS technology. Two sub processors, linear processor and order processor, are integrated to achieve tera-scale performance. In the proposed SoC architecture, the data are transferred between processors and the high bandwidth dual memory through the local media bus, which reduces the power consumption in the AHB data access. Based on the memory architecture, the maximum input data rate of the proposed image stream processor reaches 62.5 Gpixel/s, which meets the requirements for real-time HDTV image processing.\",\"PeriodicalId\":263023,\"journal\":{\"name\":\"2009 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"2015 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2009.5357149\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2009.5357149","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

一个1.0 TOPS图像流处理器,用于处理多媒体内容分析的图像处理任务,采用2.2mm2面积的90nm CMOS技术实现。两个子处理器,线性处理器和顺序处理器,集成,以实现兆级性能。在SoC架构中,数据通过本地媒体总线在处理器和高带宽双存储器之间传输,从而降低了AHB数据访问的功耗。基于该存储架构,所提出的图像流处理器的最大输入数据速率达到62.5 Gpixel/s,满足实时高清电视图像处理的要求。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Tera-scale performance image stream processor with SoC architecture for multimedia content analysis
A 1.0 TOPS image stream processor, which deals with image processing tasks for multimedia content analysis, is implemented with 2.2mm2 area in 90nm CMOS technology. Two sub processors, linear processor and order processor, are integrated to achieve tera-scale performance. In the proposed SoC architecture, the data are transferred between processors and the high bandwidth dual memory through the local media bus, which reduces the power consumption in the AHB data access. Based on the memory architecture, the maximum input data rate of the proposed image stream processor reaches 62.5 Gpixel/s, which meets the requirements for real-time HDTV image processing.
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