An efficient 21.56 Gbps AES implementation on FPGA

This paper presents novel high-speed architectures for the hardware implementation of the advanced encryption standard (AES) algorithm. Unlike previous works, which rely on look-up tables to implement the subbytes and invsubbytes transformations of the AES algorithm, the proposed design employs combinational logic only. As a direct consequence, the unbreakable delay incurred by look-up tables in the conventional approaches is eliminated and the advantage of subpipelining can be further explored. Furthermore, composite field arithmetic is employed to reduce the area requirements and different implementations for the inversion in subfield GF(2/sup 4/) are compared. In addition, efficient key expansion architecture suitable for the subpipelined round units is also presented. Using the proposed architecture, a fully subpipelined encryptor with 7 substages in each round unit can achieve a throughput of 21.56 Gbps on a Xilinx XCV 1000e-8bg560 device in nonfeedback modes, which is faster and is 79% more efficient than the fastest previous FPGA implementation known to date.