提出了一种新的钨塞腐蚀失效机制

S. Bothra, H. Sur, V. Liang
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引用次数: 28

摘要

在亚半微米的CMOS工艺技术中,常用的是插塞填充钨。随着工艺技术的缩减超过0.25 /spl mu/m一代,通孔上的金属重叠也减少了。这导致过孔没有完全被覆盖的互连线覆盖。在对这种结构的评价中,我们观察到一种新的失效机制,由于特定结构上的正电荷加速了电化学腐蚀,导致了完全未填充的通孔。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A new failure mechanism by corrosion of tungsten in a tungsten plug process
The tungsten filled via plug process is commonly used in sub-half micron CMOS process technologies. As process technologies shrink beyond the 0.25 /spl mu/m generation, the metal overlap over the via also reduces. This results in vias which are not fully covered by the overlying interconnect lines. In the evaluation of such structures, we have observed a new failure mechanism resulting in completely unfilled vias due to electrochemical corrosion accelerated by a positive charge on specific structures.
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