亚微米GC SOI mosfet的模拟性能

2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) Pub Date : 2012-03-14 DOI:10.1109/ICCDCS.2012.6188930

J. Nemer, M. de Souza, M. Pavanello, D. Flandre

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引用次数: 3

摘要

本文旨在展示GC SOI MOSFET器件与标准SOI MOS晶体管的性能，比较采用GC架构在亚微米完全耗尽SOI技术中改变通道长度所取得的改进。二维数值模拟结果表明，当轻掺杂区域长度约为100 nm时，与通道总长度无关，改善效果最好。

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Analog performance of submicron GC SOI MOSFETs

This paper aims to demonstrate the performance of GC SOI MOSFET devices in comparison to standard SOI MOS transistors, comparing the improvements achieved by the adoption of the GC architecture in a submicron fully depleted SOI technology varying the channel length. The results obtained by two-dimensional numerical simulations show that the best improvement is obtained when the length of lightly doped region length is approximately 100 nm, independently of the total channel length.

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2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)

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