12层euv超尺度环绕栅晶体管6T-SRAM的DTCO和TCAD

2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) Pub Date : 2018-09-01 DOI:10.1109/SISPAD.2018.8551632

P. Matagne, H. Nakamura, M. Kim, Y. Kikuchi, T. Huynh-Bao, Z. Tao, W. Li, K. Devriendt, L. Ragnarsson, J. Boemmels, A. Mallik, E. Altamirano-Sachez, F. Sebaai, C. Lorant, N. Jourdan, C. Porret, D. Mocuta, N. Harada, F. Masuoka

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引用次数: 1

摘要

介绍了基于50nm柱距和0.0205 um2的6T-SRAM的流程，模块步骤和关键结构元件，重点介绍了工艺挑战和创新。一种新的DTCO/TCAD方法用于探索设计空间，展示位元功能并优化工艺。特别是，垂直SGT对栅极错位非常敏感，而埋在底部的接触使得该过程不受掺杂变化和错位的影响。

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DTCO and TCAD for a 12 Layer-EUV Ultra-Scaled Surrounding Gate Transistor 6T-SRAM

A flow, module steps and key structural elements enabling a surrounding gate transistor (SGT) based 6T-SRAM with 50nm pillar pitch and 0.0205 um2 are presented, with emphasis on process challenges and innovations. A new DTCO/TCAD methodology is used to explore the design space, demonstrate the bit cell functionality and optimize the process. In particular, it is shown that vertical SGT are extremely sensitive to gate misalignment and that buried bottom contact makes the process immune to doping variations and misalignments.

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2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

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