A Low-latency Tree-based Multicast Spike Routing for Scalable Multicore Neuromorphic Chips

Application-specific architectures with multiple processing cores integrated with a three-dimensional Network-on-Chip (NoC) concept can exploit the parallelism inherent within spiking and non-spiking neural networks to provide low latency and high-bandwidth communication. One of the critical components in these NoC-based spiking architectures is the on-chip routing scheme, which allows data to be communicated between cores and also off-chip data to be transported to the cores. In this work, we present a low-latency tree-based multicast spike routing for scalable neuromorphic chips. The multicast routing, which connects parallel spiking neurons to many others residing on single or multiple neuromorphic chips, is based on a combination of tree-based multicast routing and the K-means clustering mechanism. This work is part of an ongoing project named Neuro-inspired Architecture in Hardware (NASH). The evaluation results show that the proposed algorithms demonstrate lower average latency and higher throughput when compared to the unicast based method.