{"title":"全延迟可测试顺序电路的组合部件结构简化","authors":"A. Matrosova, E. Mitrofanov, Elena Roumjantseva","doi":"10.1109/EWDTS.2014.7027068","DOIUrl":null,"url":null,"abstract":"The method of a sequential circuit design based on using mixed description of a circuit behavior has been developed by us earlier. The method provides fully delay testability of a combinational part of a sequential circuit. It is oriented to cut down the path lengths of the obtained circuits. In this paper the possibilities of a simplification of combinational parts of the sequential circuits are considered. They are based on using corrected Free BDDs instead of ROBDDs and factorizing monotonous products. Some experimental results are given.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Combinational part structure simplification of fully delay testable sequential circuit\",\"authors\":\"A. Matrosova, E. Mitrofanov, Elena Roumjantseva\",\"doi\":\"10.1109/EWDTS.2014.7027068\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The method of a sequential circuit design based on using mixed description of a circuit behavior has been developed by us earlier. The method provides fully delay testability of a combinational part of a sequential circuit. It is oriented to cut down the path lengths of the obtained circuits. In this paper the possibilities of a simplification of combinational parts of the sequential circuits are considered. They are based on using corrected Free BDDs instead of ROBDDs and factorizing monotonous products. Some experimental results are given.\",\"PeriodicalId\":272780,\"journal\":{\"name\":\"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EWDTS.2014.7027068\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EWDTS.2014.7027068","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Combinational part structure simplification of fully delay testable sequential circuit
The method of a sequential circuit design based on using mixed description of a circuit behavior has been developed by us earlier. The method provides fully delay testability of a combinational part of a sequential circuit. It is oriented to cut down the path lengths of the obtained circuits. In this paper the possibilities of a simplification of combinational parts of the sequential circuits are considered. They are based on using corrected Free BDDs instead of ROBDDs and factorizing monotonous products. Some experimental results are given.