全延迟可测试顺序电路的组合部件结构简化

A. Matrosova, E. Mitrofanov, Elena Roumjantseva
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引用次数: 0

摘要

基于混合描述电路行为的顺序电路设计方法在较早的时候已被提出。该方法提供了顺序电路的组合部分的完全延迟可测试性。它被定向以减少所获得电路的路径长度。本文考虑了对顺序电路的组合部分进行简化的可能性。它们是基于使用修正的Free bdd而不是robdd和分解单调乘积。给出了一些实验结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Combinational part structure simplification of fully delay testable sequential circuit
The method of a sequential circuit design based on using mixed description of a circuit behavior has been developed by us earlier. The method provides fully delay testability of a combinational part of a sequential circuit. It is oriented to cut down the path lengths of the obtained circuits. In this paper the possibilities of a simplification of combinational parts of the sequential circuits are considered. They are based on using corrected Free BDDs instead of ROBDDs and factorizing monotonous products. Some experimental results are given.
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