{"title":"DRAM/PCRAM混合记忆体架构的自适应页分配","authors":"W. Cheng, Pi-Chieh Cheng, Xinlun Li","doi":"10.1109/ISNE.2016.7543402","DOIUrl":null,"url":null,"abstract":"In this paper, we propose an adaptive page allocation and buffer management methodology for the hierarchical DRAM/PCRAM memory architecture. A small DRAM is used as cache of PCRAM memory to reduce leakage power consumption, and an adaptive page allocation scheme is used to make better utilization of the small DRAM capacity, such that conflict misses of DRAM are minimized under the multi-core architecture. Therefore, the number of write back to PCRAM and data migration between PCRAM and DRAM is obviously reduced. Experimental results show that our methodology is effective in improving both the energy consumption and access latency of PCRAM by 25%.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"408 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Adaptive page allocation of DRAM/PCRAM hybrid memory architecture\",\"authors\":\"W. Cheng, Pi-Chieh Cheng, Xinlun Li\",\"doi\":\"10.1109/ISNE.2016.7543402\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we propose an adaptive page allocation and buffer management methodology for the hierarchical DRAM/PCRAM memory architecture. A small DRAM is used as cache of PCRAM memory to reduce leakage power consumption, and an adaptive page allocation scheme is used to make better utilization of the small DRAM capacity, such that conflict misses of DRAM are minimized under the multi-core architecture. Therefore, the number of write back to PCRAM and data migration between PCRAM and DRAM is obviously reduced. Experimental results show that our methodology is effective in improving both the energy consumption and access latency of PCRAM by 25%.\",\"PeriodicalId\":127324,\"journal\":{\"name\":\"2016 5th International Symposium on Next-Generation Electronics (ISNE)\",\"volume\":\"408 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 5th International Symposium on Next-Generation Electronics (ISNE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISNE.2016.7543402\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISNE.2016.7543402","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Adaptive page allocation of DRAM/PCRAM hybrid memory architecture
In this paper, we propose an adaptive page allocation and buffer management methodology for the hierarchical DRAM/PCRAM memory architecture. A small DRAM is used as cache of PCRAM memory to reduce leakage power consumption, and an adaptive page allocation scheme is used to make better utilization of the small DRAM capacity, such that conflict misses of DRAM are minimized under the multi-core architecture. Therefore, the number of write back to PCRAM and data migration between PCRAM and DRAM is obviously reduced. Experimental results show that our methodology is effective in improving both the energy consumption and access latency of PCRAM by 25%.