MEGsim: gpu中图形工作负载高效仿真的新方法

Jorge L. Ortiz, David Corbalán-Navarro, Juan L. Aragón, Antonio González
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引用次数: 0

摘要

周期精确的微架构模拟器的一个重要缺点是,它们比它们所模拟的系统慢几个数量级。当模拟必须在期望的设计空间中多次重复时,这就成为一个重要的问题。在图形工作负载的特定环境中,由于必须对大量三角形进行阴影,照明和纹理来组成单个帧,因此执行周期精确模拟的要求更高。因此,模拟几分钟的电子游戏序列是非常耗时的。在本文中,我们观察到收集有关处理的顶点和原语的信息,以及着色器程序被调用的时间,使我们能够描述在给定帧上执行的活动。在此基础上,我们提出了一种新的方法来有效地模拟图形工作负载,称为MEGsim,这种方法能够通过使用一小部分选定的帧来准确地表征整个视频序列,从而大大降低了模拟时间。对于一组流行的Android游戏,我们展示了MEGsim实现了126倍的平均模拟加速,对于估计的最终统计数据获得了非常准确的结果,例如,总周期数的平均相对误差仅为0.84%,DRAM访问次数为0.99%,L2缓存访问次数为1.2%,L1 (tile缓存)访问次数为0.86%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
MEGsim: A Novel Methodology for Efficient Simulation of Graphics Workloads in GPUs
An important drawback of cycle-accurate microarchitectural simulators is that they are several orders of magnitude slower than the system they model. This becomes an important issue when simulations have to be repeated multiple times sweeping over the desired design space. In the specific context of graphics workloads, performing cycle-accurate simulations are even more demanding due to the high number of triangles that have to be shaded, lighted and textured to compose a single frame. As a result, simulating a few minutes of a video game sequence is extremely time-consuming.In this paper, we make the observation that collecting information about the vertices and primitives that are processed, along with the times that shader programs are invoked, allows us to characterize the activity performed on a given frame. Based on that, we propose a novel methodology for the efficient simulation of graphics workloads called MEGsim, an approach that is capable of accurately characterizing entire video sequences by using a small subset of selected frames which substantially drops the simulation time. For a set of popular Android games, we show that MEGsim achieves an average simulation speedup of 126×, achieving remarkably accurate results for the estimated final statistics, e.g., with average relative errors of just 0.84% for the total number of cycles, 0.99% for the number of DRAM accesses, 1.2% for the number of L2 cache accesses, and 0.86% for the number of L1 (tile cache) accesses.
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