用于空间应用的低功耗0.25 /spl mu/m ASIC技术

N. Haddad, R. Berger, R.D. Brown
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引用次数: 2

摘要

宽带空间通信的出现加速了对高密度、高性能、低功耗抗辐射技术的需求。研制并演示了0.25 /spl μ m CMOS辐射增强专用集成电路库。该库与最先进的耐辐射商业铸造制造兼容,并提供了目前生产中最新的辐射硬化技术的重大进步。该库支持70 ps延迟,0.02 /spl mu/W/Gate/MHz功耗和高达7M的栅极/芯片密度,在自然空间环境下实现200 Krad (Si)的扰流率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Low power 0.25 /spl mu/m ASIC technology for space applications
The advent of broadband space communication has accelerated the need for high density, high performance, low power radiation hardened technology. A 0.25 /spl mu/m CMOS radiation enhanced ASIC library was developed and demonstrated. The library is compatible with state-of-the-art radiation tolerant commercial foundry fabrication and offers a significant advancement over the latest radiation hardened technology now in production. The Library supports 70 ps delay, 0.02 /spl mu/W/Gate/MHz power consumption and up to 7M gate/chip density, and achieves an upset rate of <1E-10 upset/bit/day in the 90% geosynchronous environment. The technology is latch-up immune and supports a total dose of >200 Krad (Si) in the natural space environment.
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