Architecture-Based Software Designs for SDR's

Hybrid embedded systems, which employ parallel processing using FPGAs, are gaining momentum as they add significant performance boost for applications such as wireless communication. Our goal is to develop a flexible infrastructure that allows FPGA-based processing to be combined with CPU-based processing. Our conclusions are that there is little difference in area or performance between NoC organizations, particularly for a small number of processing endpoints, that some space is saved by time-interleaved signal processing blocks but that partial reconfiguration is likely to lead to gross inefficiencies. Based on this experience, we are focusing our FPGA design effort on developing software that can simplify and automate the process of developing SDR signal processing chains. This software relies on standard interfaces and a synthesis as a service organization to reduce the complexity of constructing custom FPGA bitfiles rather than mechanisms to dynamically reconfigure FPGA's.