Analysis of Performance of Instruction Pipeline with Transactional Slice Mechanism in CMP

Instruction throughput is one of the most important metric for improving the performance of systems and instruction pipeline play a major role in increasing this factor. But still, satisfactory performance of instruction pipeline is not yet achieved, due to some limitations, particularly branch instructions. These branch instructions restrict the full utilization of instruction pipeline. Therefore, the challenge is to reduce those branch penalties which cause significant degradation in performance of instruction pipelining. One optimal solution of reducing branch penalties is Transactional Slice (TS) mechanism with no branch overhead. The main objective of this research is the accurate size estimation for each transactional slice (TS), which can easily be incorporated into instruction pipeline. In previous research, the size of TS blocks estimated by using only one benchmarks suites has been investigated. However in this research article, the experiments have been conducted with three benchmark workloads to accomplish the accurate size estimation based on results from these workloads. From the results, we can also analyze the frequency of branch occurrence in instruction pipeline. The given mathematical model, examines the timing and pipeline behavior for in-order pipeline.