Alberto Gatti, G. Spiazzi, A. Gerosa, A. Neviani, A. Bevilacqua
{"title":"用于低功耗应用的130纳米CMOS双输入极性DC-DC转换器","authors":"Alberto Gatti, G. Spiazzi, A. Gerosa, A. Neviani, A. Bevilacqua","doi":"10.1109/ESSCIRC.2019.8902862","DOIUrl":null,"url":null,"abstract":"This letter presents a dc–dc converter realized in a 130-nm CMOS technology that features the same conversion gain as a standard boost converter, but it is able to process a dual polarity input with a magnitude down to 60 mV. The circuit prototypes feature a regulated output voltage of 1.2 V, an efficiency up to 88% and a maximum output power of 6 mW, while limiting the number of required off-chip components to two capacitors and one inductor.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 130-nm CMOS Dual Input-Polarity DC–DC Converter for Low-Power Applications\",\"authors\":\"Alberto Gatti, G. Spiazzi, A. Gerosa, A. Neviani, A. Bevilacqua\",\"doi\":\"10.1109/ESSCIRC.2019.8902862\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This letter presents a dc–dc converter realized in a 130-nm CMOS technology that features the same conversion gain as a standard boost converter, but it is able to process a dual polarity input with a magnitude down to 60 mV. The circuit prototypes feature a regulated output voltage of 1.2 V, an efficiency up to 88% and a maximum output power of 6 mW, while limiting the number of required off-chip components to two capacitors and one inductor.\",\"PeriodicalId\":402948,\"journal\":{\"name\":\"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2019.8902862\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2019.8902862","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 130-nm CMOS Dual Input-Polarity DC–DC Converter for Low-Power Applications
This letter presents a dc–dc converter realized in a 130-nm CMOS technology that features the same conversion gain as a standard boost converter, but it is able to process a dual polarity input with a magnitude down to 60 mV. The circuit prototypes feature a regulated output voltage of 1.2 V, an efficiency up to 88% and a maximum output power of 6 mW, while limiting the number of required off-chip components to two capacitors and one inductor.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
