D. Kostygov, A. Gruzlikov, N. Kolesov, M. Tolmacheva
{"title":"一种高效节能的片上多核控制系统","authors":"D. Kostygov, A. Gruzlikov, N. Kolesov, M. Tolmacheva","doi":"10.1109/CTS48763.2019.8973274","DOIUrl":null,"url":null,"abstract":"An approach to designing fault-tolerant and power-efficient multicore systems on chip for real-time control is proposed. It is assumed that a multicore system has a reserve cores on the chip, allowing for additional information processing. The approach is based on the rules of introducing redundancy aimed at reducing power consumption and the principles of system-level fault diagnosis, making it possible to decentralize the system recovery in case of failure.","PeriodicalId":118995,"journal":{"name":"2019 III International Conference on Control in Technical Systems (CTS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Power Efficient Multicore Control System on Chip\",\"authors\":\"D. Kostygov, A. Gruzlikov, N. Kolesov, M. Tolmacheva\",\"doi\":\"10.1109/CTS48763.2019.8973274\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An approach to designing fault-tolerant and power-efficient multicore systems on chip for real-time control is proposed. It is assumed that a multicore system has a reserve cores on the chip, allowing for additional information processing. The approach is based on the rules of introducing redundancy aimed at reducing power consumption and the principles of system-level fault diagnosis, making it possible to decentralize the system recovery in case of failure.\",\"PeriodicalId\":118995,\"journal\":{\"name\":\"2019 III International Conference on Control in Technical Systems (CTS)\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 III International Conference on Control in Technical Systems (CTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CTS48763.2019.8973274\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 III International Conference on Control in Technical Systems (CTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CTS48763.2019.8973274","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Power Efficient Multicore Control System on Chip
An approach to designing fault-tolerant and power-efficient multicore systems on chip for real-time control is proposed. It is assumed that a multicore system has a reserve cores on the chip, allowing for additional information processing. The approach is based on the rules of introducing redundancy aimed at reducing power consumption and the principles of system-level fault diagnosis, making it possible to decentralize the system recovery in case of failure.