The Extremely Large 2.5D Molded Interposer on Substrate (MIoS) Package Integration - Warpage and Reliability

Advanced package technology has been developed rapidly to meet a demand of the high end application such as AI and datacenter. 2.5D silicon interposer technology has been focused as the solution, for high end applications because of its heterogeneous device integration compatibility: high bandwidth memories (HBMs), logic devices or functional chiplets. In this study, a 2.5D structure package called Molded Interposer on Substrate (MIoS) with an extremely large silicon interposer (>2800mm2) on the $85\times 85\text{mm}^{2}$ body size assembled with 2-ASICs and 8-HBMs was demonstrated successfully for higher chip integration capability. Also, the key challenges of extremely large size 2.5D MIoS package such as warpage of the molded interposer (MIP) module and high level of reliability subjected to thermo-mechanical stress were investigated. MIP warpage was simulated by finite element method (FEM) and controlled the warpage difference between MIP and substrate below 50um at solder melting temperature. As a result, the number of 60K bumps obtained the good joint quality during reflow bonding process. The package reliability was evaluated under thermal cycle test (−55∼125°C) for optimizing the stress induced by the mismatch of thermal expansion (CTE) of components: substrate, underfill, ring frame materials and epoxy mold compound (EMC). The primary failure modes were underfill crack and EMC crack at the corner of devices at the early stage but, through a study on components material properties, package level reliability was improved.